1. Technical Field
The present invention relates to latched serial communications and, in particular, to circular elasticity buffers. Still more particularly, the present invention provides a method, apparatus, and program for shift control of circular elasticity buffers.
2. Description of the Related Art
The internal clock for a device is based on a phased lock loop (PLL) with its own clock generator. This is used when transmitting data onto the serial link. When receiving serial data, this data must be latched based on a clock derived from the received data itself. Although the input clock is normally a fixed rate, it can differ slightly from the internal clock due to accepted manufacturer tolerances. Over time, the differences in the clocks can cause data corruption.
Clock skew management is handled by an elasticity buffer. The elasticity buffer circuitry is required to absorb the differences in these clock frequencies by either deleting “clock skew” fill words to keep the elasticity buffer from overflowing, or by inserting these fill words into the data stream to keep the elasticity buffer from underflowing. Fill words are usually pre-defined word values known as primitives, for example in the Serial ATA and Serial Attached SCSI an ALIGN primitive is defined as a fill word, in Fibre Channel, an IDLE primitive is defined as a fill word. The management logic for the elasticity buffer usually involves complex math equations as well as possible latency issues caused by taking into account the differences with the elasticity read and elasticity write clock domains.
Most elasticity buffers are circular, meaning that they start inputting data at address 0 (zero) and then increment the write address pointer. Once the last address has been written to, the address pointer “rolls-over” back to address 0. The same is true with the read pointer. Now take into account that both pointers are running on separate clocks. The logic associated with determining if the elasticity buffer is filling up or emptying is usually determined by how many spaces are available to write data into. This involves some type of math function implemented in the logic to determine how full or how empty the elasticity buffer actually is. For example, the math function may be as follows:space—available=write—pointer—address[3:0]−read—pointer—address[3:0]
The disadvantage of using a math function, as above, is that much more logic is required to determine whether the address pointers have “rolled-over.” Since the address pointers are operating on different clocks, in order to keep the address values from being in a meta-stable state, the address values must be synchronized from one clock domain to another. This causes additional logic and latency, which will force the designer to make the elasticity buffer larger to account for the worst case latency.
Therefore, it would be advantageous to provide an improved management logic for an elasticity buffer.